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cb01810's avatar
cb01810
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4 years ago
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Cyclone II Quartus Legacy Support

I've been asked by a client to make a design change to a Cyclone II design. Long-term, the product will be migrated to a newer Intel FPGA. The Quartus versions on the web do not support Cyclone II;...
  • cb01810's avatar
    cb01810
    4 years ago

    Please ignore post. One Intel download page only cites repositories that go back to 13.2, but this link brings you to a page that includes versions back to 2.2 -- Yikes!

    Download Center for FPGAs (intel.com)

cb01810's avatar
cb01810
Icon for New Contributor rankNew Contributor
4 years ago

Please ignore post. One Intel download page only cites repositories that go back to 13.2, but this link brings you to a page that includes versions back to 2.2 -- Yikes!

Download Center for FPGAs (intel.com)

Jaguar1's avatar
Jaguar1
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4 years ago

I'm the same boat as the original poster. I've registered and logged in, but still only see Quartus version13.1 and newer. is anyone else able to see and download the older versions?

    • Jaguar1's avatar
      Jaguar1
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      4 years ago

      Thanks ak6dn. I installed it and the first thing I noticed is lack of support for the SOPC build, which gets to the heart of my problem, which is core IP upgrades. I've already tried some earlier versions, to no avail. My issue is that the cores were generated by Quartus 7 (or 6, depending on whether I believe the output files or the SOPC builder opening dialog). I think this means I have to upgrade the cores starting with with either the last version of Quartus supporting the System Wizard or the earliest version supporting the SOPC builder (versions 6 and 7 which I was hoping to download and try). The main upgrade issue appears to be the DDR2 core. See below for an excerpt the generation report, ddr2_sdram.html).

      All the generated files are present but I can't seem to get it to install using the SOPC builder. Qsys is even worse and omits all the cores during the upgrade. As a last resort, I suppose I can regenerate the library module with the "new component" option and add it back to the design, but I was hoping for an option that gets us closer to the original HDL as the verification and validation starting point.

      Potentially complicating matters, judging from experimenting with different Quartus versions, there seems to be a point where the Quartus DDR2 core (I don't remember exactly but sometime between versions 10 and 12) where Quartus no longer supports Cyclone II, but before that Quartus version, this particular DDR2 core is not available. That's why I wanted to try version 7. Appreciate any further comments or suggestions.

      Generation Report - DDR2 SDRAM Controller v7.0
      Entity Name ddr2_sdram_auk_ddr_sdram
      Variation Name ddr2_sdram
      Variation HDL Verilog HDL
      Output Directory (omitted)

      File Summary

      The MegaWizard interface is creating the following files in the output directory:
      File Description
      ddr2_sdram.v A MegaCore® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.
      ddr2_sdram_bb.v Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.
      [etc etc.]
      • cb01810's avatar
        cb01810
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        4 years ago

        I ran into a similar problem where a design I built in QSYS or System builder wouldn't compile. It was quite a while ago, so I'm not sure I remember all the details. I had to go in and "recompile" all the custom peripherals inside System Builder so that they were brought up to the same Quartus version. I use quotes around recompile bc I don't think that's the terminology that Quartus used. Again, this isn't exactly what you're seeing but perhaps it will send you in a useful direction.