From the device datasheet Cyclone II has 4 PLL, and I need to generate four 250MHz clocks with 0 degree, 90 degree, 180 degree and 270 degree phase shift. The input clock is 50MHz. But the altpll function only has 3 output (c0-c2). How to access the other 3 pll ?

Strictly NO !, you can't "shift 180°" with NOT gate because gates introduce a delay, so 180° is NOT guaranteed by this way.

just instantiate others "altpll", I think.

You can do it with two PLL output clocks as 180° = 0° inverted and 270° = 90° inverted

What about rising_edge( clock ) and falling_edge( clock ) then? and DDR input blocks? See page 2-9 of the Cyclone II datasheet: chapter 2. cyclone ii architecture (http://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf)

You can do a NOT gate or rising/falling edge. There is an inversion as the clock goes into the LAB that has negligible delay. It shouldn't be a problem at all and only uses two globals. (Now, most of the time I see people do this is to oversample some incoming signal. Ideally that external data comes in and feeds four FFs clocked by these different clocks, all in the same LAB. The LAB-wide clock signal will hurt you here, in that you can't get four clocks into a single LAB, so the FFs get spread out and you get more skew. This is true whether you invert the clocks or had four separate clocks. Of course, it depends on your rates if that's a problem or not)

Cyclone II: PLL | Altera Community

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Altera_Forum
Honored Contributor
11 years ago
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Once again: you don't need two PLLs to generate the 4 clocks: 0°, 90°, 180°, 270°. As Rysc confirmed you can use just one PLL with two clocks 0° and 90° and either use a 'not' operator or use falling_edge() in VHDL or negedge in Verilog to get the 180° and 270°.
As FvM indicates: using 2 PLLs wil necessitate connecting the external clock reference to 2 pins on the FPGA which in Cyclone II are located on the opposite sides. This will add about 150 to 200 ps skew between the outputs of the two PLLs. Also the two PLLs are located on different sides of the FPGA, adding more skew.
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ok...got It. Now I need to modify my Verilog code to work on just with two clocks. Thanks for all of the comments.

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Cyclone II: PLL

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