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Honored Contributor
Honored ContributorCyclone II: PLL
From the device datasheet Cyclone II has 4 PLL, and I need to generate four 250MHz clocks with 0 degree, 90 degree, 180 degree and 270 degree phase shift. The input clock is 50MHz. But the altpll fun...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Did you miss the table pll clock input pin connections in the Cyclone II Device Handbook? The problem with Cyclone II is that PLLs can be only driven by specific input pins, to use multiple PLLs, the clock source must be wired to different sides of the FPGA. --- Quote End --- Ok..i will recheck again in the device handbook. Just one more question, can two pll be driven by the same source clock at the same time ?
