Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Cyclone II: PLL

From the device datasheet Cyclone II has 4 PLL, and I need to generate four 250MHz clocks with 0 degree, 90 degree, 180 degree and 270 degree phase shift. The input clock is 50MHz. But the altpll fun...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Did you miss the table pll clock input pin connections in the Cyclone II Device Handbook?

The problem with Cyclone II is that PLLs can be only driven by specific input pins, to use multiple PLLs, the clock source must be wired to different sides of the FPGA.