Cyclone II: PLL

You can do a NOT gate or rising/falling edge. There is an inversion as the clock goes into the LAB that has negligible delay. It shouldn't be a problem at all and only uses two globals.

(Now, most of the time I see people do this is to oversample some incoming signal. Ideally that external data comes in and feeds four FFs clocked by these different clocks, all in the same LAB. The LAB-wide clock signal will hurt you here, in that you can't get four clocks into a single LAB, so the FFs get spread out and you get more skew. This is true whether you invert the clocks or had four separate clocks. Of course, it depends on your rates if that's a problem or not)