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Honored Contributor
Honored ContributorCyclone II: PLL
From the device datasheet Cyclone II has 4 PLL, and I need to generate four 250MHz clocks with 0 degree, 90 degree, 180 degree and 270 degree phase shift. The input clock is 50MHz. But the altpll fun...
Altera_ForumHonored Contributor
Honored ContributorWhat about rising_edge( clock ) and falling_edge( clock ) then? and DDR input blocks?
See page 2-9 of the Cyclone II datasheet: chapter 2. cyclone ii architecture (http://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf)
