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Is it not possible to configure input and output timing when using the classical timing analyzer? I'm using Quartus II 7.1
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Even though TimeQuest has been enhanced since QII 7.1, it was the preferred timing analyzer for new designs even then. Even in QII 8.0 you may still use the Classic Timing Analyzer for device families that allow it. As I mentioned before, pay attention to what the "Description" field in the Fitter Settings dialog box says for "Optimize hold timing". The description might not have been as detailed about the behavior in QII 7.1, but the 7.1 behavior with the Classic Timing Analyzer was probably the same as described for 8.0 (the behavior with TimeQuest is what I remember changing).
This is the QII 8.0 "Description" text:
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Allows the Fitter to optimize hold time by adding delay to the appropriate paths. The Optimize Timing option must be turned on in order for this option to work. If you are using the Classic Timing Analyzer and specify the I/O Paths and Minimum tpd Paths setting, which is the default setting, the Fitter optimizes hold timing only for the following assignments: th assignments from an I/O pin to a register, Minimum tco assignments from a register to an I/O pin, and Minimum tpd assignments from an I/O pin or register to an I/O pin or register. All other I/O pin assignments, such as Minimum Delay, Input Minimum Delay, and Output Minimum Delay, are not optimized. If you are using the TimeQuest Timing Analyzer, and specify the I/O paths and Minimum tpd Paths setting, which is the default setting, all assignments involving I/O pins are optimized. Specifying the All Paths setting directs the Fitter to optimize the hold time of all paths. Turning off this option directs the Fitter not to optimize the hold time of any paths.
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