Cyclone II: how to delay output to pin?

First you need to follow jakobjones' advice. Fully constrain the setup and hold requirements for both inputs and outputs, preferably using set_input_delay and set_output_delay -max and -min in TimeQuest.

In addition to giving the Fitter the I/O timing constraints, you might need to set "Optimize hold timing" to "All paths" on the "Fitter Settings" page of the Settings dialog box. The "Description" field in the dialog box in QII 8.0 sounds like "All paths" is no longer necessary for TimeQuest, but in the past you had to use "All paths" to get this optimization to apply to hold for I/O constrained with set_input_delay -min and set_output_delay -min. "All paths" is still needed for certain kinds of Classic Timing Analyzer I/O constraints.

If the amount of additional delay needed to satisfy the set_output_delay -min requirement (corresponds to the minimum tco) isn't too much and if the output register is not in the I/O cell, the hold optimization will result in routing delay being inserted.

The Fitter will try to set the input and output delay chains to an appropriate value to meet both setup and hold requirements, but you might need to control these delay chains manually through the Assignment Editor to increase your output delay and reduce your input delay. To slow the output in Stratix III, for example, use the "D5 Delay" or the "D6 Delay" settings (a figure in the Stratix III handbook shows where D5 and D6 delay chains are in the I/O structure). The Assignment Editor will call this delay something else for other device families.

If you need to create a larger minimum delay than the Fitter does well by automatically inserting routing, then manually inserting a chain of LCELLs might be the best way. Be sure to analyze the timing for all timing models. You always should do this, but it is even more important when trying to create a minimum delay with logic resources that might have a lot of variation over process/voltage/temperature. You might need to enable "Optimize fast-corner timing" in the Fitter Settings to get good results with the fast timing model.

If you can phase shift the clock used by the I/O registers (even if you have to use an additional PLL output for just this), then adjusting the clock can let you fine tune the tradeoff between setup and hold.