Looks ok to me, very similar to a board I have that uses the EP2C20 device with an EPCS4 config device.
It uses normal (slower) AS active serial mode, so both MSEL1 and MSEL0 are wired to GND.
JTAG wiring is connected to the FPGA only; programming the config device EPCS4 is done thru JTAG using the SFL module instantiated in the code as shown below.
When the board is first powered on with a blank config device and an unconfigured FPGA, only the FPGA is in the JTAG chain.
I then load a .sof ram image into the FPGA that has the SFL module in it, and rescan the JTAG chain.
This will then allow the config EPCS4 to now appear in the JTAG chain (so two devices are present, the FPGA and the EPCS4).
At this point I can then program the EPCS4 with a .jic file that has the FPGA program image.
Here is the .cdf (chain descriptor file) I use to do the programming with the Altera Programmer:
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EP2C20F484)
Path("") File("PDP8.sof")
MfrSpec(OpMask(1) SEC_Device(EPCS4)
Child_OpMask(1 3) SFLPath("PDP8.jic"));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;
Altera SFL serial flash loader instantiated in FPGA top level verilog module:
// Altera Serial Flash Loader module
// Allows external JTAG access to the serial config eeprom for programming
sfl sfl
( .asdo_in (1'b0), // not used
.dclk_in (1'b0), // not used
.ncso_in (1'b0), // not used
.noe_in (1'b0), // always enabled
.asmi_access_granted (1'b1), // external JTAG access always
.asmi_access_request (), // not used
.data0_out () // not used
);
Also you do know you have to use Quartus 13.0sp1 or 13.1 for development (still downloadable) as those are the last versions that support the CycloneII series.
Which begs the question why are you designing a NEW board with the CycloneII series? It is basically EOL and obsolete at this point.
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