Cyclone II Configuration Basics

Hi,

the EPCS devices are compatible with all the FPGAs which support Active Serial configuration. In fact, EPCS are plain serial flash.

A common setup is to have AS+JTAG, without any pin headers in the AS signals, only for the JTAG signals.

This requires use of JTAG indirect programming to read/write the EPCS but it's more practical than having two sets of pin headers for the ByteBlaster.

The document you want is the Cyclone III handbook configuration section.

http://www.altera.com/literature/lit-cyc3.jsp

I don't think there's any documentation on designs which support more than one configuration scheme (other than JTAG) though.

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Hi,

the EPCS devices are compatible with all the FPGAs which support Active Serial configuration. In fact, EPCS are plain serial flash.

A common setup is to have AS+JTAG, without any pin headers in the AS signals, only for the JTAG signals.

This requires use of JTAG indirect programming to read/write the EPCS but it's more practical than having two sets of pin headers for the ByteBlaster.

The document you want is the Cyclone III handbook configuration section.

http://www.altera.com/literature/lit-cyc3.jsp

I don't think there's any documentation on designs which support more than one configuration scheme (other than JTAG) though.

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Thank you very much for the help. It looks like Figure 9-30 describes the indirect JTAG configuration, is that correct?

Why would I need two connectors otherwise? Perhaps one to configure the FPGA directly (during development) and one to program the EPCS4?

It also appears that the indirect method requires changes to the project in Quratus. I would rather avoid this if possible........

Thanks

Rich

Yes, it is correct.

I don't know of a good use case for having both the JTAG and AS connectors. Usually just having the JTAG one is enough.

Read/Writing the EPCS is faster via the AS connector though.

You don't need to make any changes, you can just that the .SOF file and make a .JIF file for indirect programming.

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Yes, it is correct.

I don't know of a good use case for having both the JTAG and AS connectors. Usually just having the JTAG one is enough.

Read/Writing the EPCS is faster via the AS connector though.

You don't need to make any changes, you can just that the .SOF file and make a .JIF file for indirect programming.

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I am looking at this app note:

and it looks more involved than what I am willing to do. I think, because I don't want to brick my first prototype, I will stick with AS programming of the EPCS device.

Any use in bringing out the JTAG anyway?

Rich

I'm not sure at which app note you're looking (although I suspect) but trust me on this: you just fire up the "Convert Programming File" dialog, make a .JIC from the .SOF and program it using the Programmer tool. No changes to your design are needed.

JTAG allows you to download configurations directly into the FPGA (much faster than programming the PROM), to use SignalTap for debugging, etc.

Quite honestly, not having JTAG is... insane.

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I'm not sure at which app note you're looking (although I suspect) but trust me on this: you just fire up the "Convert Programming File" dialog, make a .JIC from the .SOF and program it using the Programmer tool. No changes to your design are needed.

JTAG allows you to download configurations directly into the FPGA (much faster than programming the PROM), to use SignalTap for debugging, etc.

Quite honestly, not having JTAG is... insane.

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I think I see the misunderstanding. JTAG will program the FPGA directly which is fine but if you want to program the EPCS serial flash device through JTAG then you need to go through a lot as described in this app note (I forgot the link last time):

http://www.altera.com/literature/an/an370.pdf

I may be able to squeeze in both connectors. In later revs perhaps I can get rid of the one for AS programming after I get the indirect programming working..

Rich

The app note makes it look worse than it usually is, because it's describing some of the gruesome details.

To write an EPCS through JTAG, you must first download into the FPGA a configuration which includes the SFL function.

There are two options for this:

a) you do not include the SFL in your design and download an Altera provided configuration which just implements the SFL into the FPGA whenever you want to program the EPCS

b) you include the SFL into your design

What most people do is use option "a)".

Then we just apply what's described in the "Converting .sof to .jic Files in the Quartus II Software" and "Programming Serial Configuration Devices Using the Quartus II Programmer and .jic Files" parts of the app note.

It just requires a few more clicks to generate the programming file.

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What most people do is use option "a)".

Then we just apply what's described in the "Converting .sof to .jic Files in the Quartus II Software" and "Programming Serial Configuration Devices Using the Quartus II Programmer and .jic Files" parts of the app note.

It just requires a few more clicks to generate the programming file.

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+1 here.

It takes a minute or two to produce the JIC the first time then you can safe the COF for the convert programming tool.

I then add a script to the design flow so this happens automatically when I build the device.

No extra hassle and just wiring to the JTAG header usually allows much more compact (/noise immune) routing.

Nial.