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Just checked the schematic part, I cant beleave how simple these things are to setup :)
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Still, people do get it wrong ... as recent threads show. Here's few warnings;
1) Connection all VCCIO power banks, even if you do not use pins on those banks.
2) If the package has a power-pad (underneath it), make sure to connect it.
3) Connect all the device-specific programming pins appropriately, eg., nCE, MSEL[], nCONFIG, nSTATUS, CONF_DONE, (optional INIT_DONE), etc.
4) Connect the JTAG interface. Use a shrouded header for the PCB layout, as it helps to get the cable orientation correct. Make sure you leave enough room around the part.
5) Include a power-on-reset supervisor IC external to the FPGA. Its nice for producing a nice clean reset signal. You can usually connect a push-button input into the reset supervisor IC, and it'll debounce the signal for you.
Look at other peoples designs, try to understand them.
Cheers,
Dave
Honored Contributor
