Forum Discussion
AMaat
New Contributor
New ContributorCyclone 5 SoC - HPS DDR - 16 Bit SDRAM on other bytelanes than 0 and 1
Hello, i'm currently designing a board with a Cyclone V SE with a single 16 bit DDR3 connected to Bytelanes 0 and 1. in order to simplify the layout, the layouter requests to use other bytelanes in...
BoonT_Intel
Frequent Contributor
Frequent ContributorHi,
Yes, it should be ok as you can use any available DQ/DQS group (byte) from the FPGA to build your x16 interface.
Anyway, as mentioned please try to fit it in Quartus. If quartus does not complaint then it is good to go. 😉
