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AMaat's avatar
AMaat
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6 years ago

Cyclone 5 SoC - HPS DDR - 16 Bit SDRAM on other bytelanes than 0 and 1

Hello, i'm currently designing a board with a Cyclone V SE with a single 16 bit DDR3 connected to Bytelanes 0 and 1. in order to simplify the layout, the layouter requests to use other bytelanes in...
AMaat's avatar
AMaat
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6 years ago

Hello,

thanks for your reply,

Currently DDR DQ0-7 nets ('bytelane 0') is referring to HPS_DQS_0 and HPS_DQS#_0 (Pins R17/R16) and DDR DQ8-15 nets ('bytelane 1')is referring to HPS_DQS_1 and HPS_DQS#_1 (Pins R19/R18)

The layouter requests to connect DDR DQ0-7 nets ('bytelane 0') is referring to HPS_DQS_1 and HPS_DQS#_1 (Pins R19/R18) and and DDR DQ8-15 nets ('bytelane 1')is referring to HPS_DQS_4 and HPS_DQS#_4 (Pins V18/V17)

i'll ask the quartus colleague to check this in the tooling