Cyclone 5 SoC - HPS DDR - 16 Bit SDRAM on other bytelanes than 0 and 1

Hello,

thanks for your reply,

Currently DDR DQ0-7 nets ('bytelane 0') is referring to HPS_DQS_0 and HPS_DQS#_0 (Pins R17/R16) and DDR DQ8-15 nets ('bytelane 1')is referring to HPS_DQS_1 and HPS_DQS#_1 (Pins R19/R18)

The layouter requests to connect DDR DQ0-7 nets ('bytelane 0') is referring to HPS_DQS_1 and HPS_DQS#_1 (Pins R19/R18) and and DDR DQ8-15 nets ('bytelane 1')is referring to HPS_DQS_4 and HPS_DQS#_4 (Pins V18/V17)

i'll ask the quartus colleague to check this in the tooling