Cyclone 5 SoC - HPS DDR - 16 Bit SDRAM on other bytelanes than 0 and 1

Hi Sir,

Is the bytelane that you saying here referring to HPS_DQS_0 and HPS_DQS_3 in the pin-out file?

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html

If yes, you suppose can place the DQ pin into these groups as they are HPS DQ pin. Anyway, after you place it, try to fit with quartus full compilation to confirm.