Forum Discussion
AMaat
New Contributor
New ContributorCyclone 5 SoC - HPS DDR - 16 Bit SDRAM on other bytelanes than 0 and 1
Hello, i'm currently designing a board with a Cyclone V SE with a single 16 bit DDR3 connected to Bytelanes 0 and 1. in order to simplify the layout, the layouter requests to use other bytelanes in...
BoonT_Intel
Frequent Contributor
Frequent ContributorHi Sir,
Is the bytelane that you saying here referring to HPS_DQS_0 and HPS_DQS_3 in the pin-out file?
https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html
If yes, you suppose can place the DQ pin into these groups as they are HPS DQ pin. Anyway, after you place it, try to fit with quartus full compilation to confirm.
