Cyclone 5 custom board PLL issues

I could not solve the problem yet but I found the following:

For the input clk 50Mhz, if I only used with its PLL, I find that it utilizes the PLL FRACTIONALPLL_X0_Y56. In this case, the PLL does not lock and not output clk from the PLL.

When I add one other PLL, I find that the 50MHz clk utilizes the PLL FRACTIONALPLL_X0_Y74. In this the first PLL works but the newer one does not work.

I searched online on how to force one clk to use a certain pll, and I used the following constraint in the assignment editor,

(NOTE: The design has only one PLL connected to the 50MHz input clock and )

set_location_assignment FRACTIONALPLL_X0_Y74_N0 -to "pll50:inst1|pll50_0002:pll50_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL"

In this case the PLL worked and the output clk is generated.

btw, this problem happens in two boards that we created.

any help?