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Altera_Forum's avatar
Altera_Forum
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11 years ago

Cyclone 5 : TCO, TSU, TH parameters for time quest analysis

Hi, I'm working on DE1 board with a cyclone V FPGA to make convolution.

I'would like tu use Time quest analysis timing and write a constraint file but i've didn't found any information on :

TCO (time to output), TSU (setup time), TH (hold time) .

I searched in cyclone 5 datasheet and cyclone5_handbook.

But i've found information for cyclone 2 => https://www.altera.com/en_us/pdfs/literature/hb/cyc2/cyc2_cii51005.pdf.

Can you help me ?

Thanks a lot,

Thomas

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    fpga tSU/tH at inputs and tCO at output is configurable. Once you enter external device/board delay values you get a pass/fail plus fpga parameters

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Ok, I though that i had to specifie TSU TH for internal Flip Flop but in fact Time quest already knows these value.

    Thanks Kaz ;)