Cyclone 4 Jtag - with VHDL

The megawizard generates VHDL or Verilog, but it's just a wrapper around a primitive which you can't change. You can hook up your own logic to the user port of the tap controller.

SVF is a file format (Serial Vector Format) which you can use to specify data to scan into the data and instruction registers.

You can also write patterns to the FTDI directly, but this is at a even lower level and you have to generate bit sequences to toggle tdi/tms to traverse the tap controller states.

But as I said altsource_probe is probably the easiest way. Come to think of it you can actually see how this is done in some of the open source bitcoin miners. Take a look at virtual_wire.v in git://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner.git. You can find tcl functions to read the probe in jtag_comm.tcl.