Cyclone 3 vs Cyclone 3 LS Power Dissipation

Yea, when I did the initial recompile on the LS part it failed due to the invalid pin assignments. Just to see if my design would compile I removed my pin QSF file. I was able to recompile and all the I/O was not mapped but have the default 2.5v/8mA values.

The compile report still accounts for the same# of pins as on the 3 and comparing the log files I'm not seeing any optimized parts of the design. Comparing LE usage the LS compile used 0.2% more which I'm disgarding as an issue as there are MegaCore components and I would'nt expect a 1:1 copy across the families (I'm in the process of getting a gate level verification of the port).

I'm not necissarly looking to pick through the design to see if a block on the 3 ran at higher power than the LS, more so trying to understand what's going on in general that the LS runs at a lower static power in worst case situations than the 3 (atleast according to the static power of the EPE and PowerPlay). Is it just physical design advancements?