Forum Discussion
Altera_Forum
Honored Contributor
13 years agoOne thought is to write a small verilog or vhdl module that will drive the SPI lines, and be controlled by a FSM. The data from the Microchip CAN chip would then be placed into data into a small RAM, that would effectively be dual port. Off chip access by an external uC could be done this way, or simply write the logic to interface to SOPC/Qsys.
Fundamentally, if you want to removed the interrupt burden on the processor, doing the design in HDL always seems to be best. -James