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Altera_Forum
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16 years ago

Cyclone 3 DDR2 controller - capture clock FIFO

Hello, I'm using the Cyclone III 3C120 eval.board to evaluate a design for a customer. I am planning to use my own DDR2 controller using a capture clock, in a similar way to what it's explained...
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Altera_Forum
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16 years ago

Thanks for your quick response Jake,

But how do u know when to expect the data? I suppose you either:

a) use DQS as an input (Altera doesn't use it when using the capture clock, so there must be another way).

b) use a pipelined version of the RD command (issued in the system clock domain) then transfer it to the capture clock domain, which doesn't seem safe as you need to cross a clock domain which could add/delete an extra clock cycle in case of metastability.

I've had a look at the Verilog code of Altera's DDR controller, unfortunately I'm a VHDL guy and can't follow it... :(

Regards,

-Ulises