Honored ContributorHi!
I draw a simple PLL using altpll setting with two frequency generate which are in 100Mhz and 500Mhz. however, I found that during compiling process, there is an error saying that target device can only support output frequency of 360MHz for this combinational I/O standard.... May I know is there any other way to generate more than 360MHz output frequency using Cyclone 2 in FPGA board? TQ
Honored ContributorThe maximum frequency on an I/O pin depends on the chip speed grade and the I/O standard used. Have a look on table 5-45 (pages 5-48 to 5-41) of this document (http://www.altera.com/literature/hb/cyc2/cyc2_cii51005.pdf). 500MHz is unattainable.
Honored Contributorcritical warning: output pin "da_clkp" (external output clock of pll "pll:inst|altpll:altpll_component|pll_altpll:auto_generated|pll1") uses i/o standard 3.3-v lvcmos, has current strength 2ma, output load 0pf, and output clock frequency of 90 mhz, but target device can support only maximum output clock frequency of 64 mhz for this combination of i/o standard, current strength and load;
when i compile my project ,there is the warning above,the pattern of the device is ep3c40f324,and the software is quartus ii 8.1.how can i deal with it? thank you!Honored ContributorIncrease the current strength on that pin. 2mA is perhaps too low for that frequency.
Honored Contributorsorry to tell you that the maximum current strength is 2mA,so i can't do it you tell me !
but when i set maximum current strength ,the result is the same as above，thank you！
