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ervoL
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6 years ago

Cyclone 10LP DDIO extra one clock latency

Hi! I am using Cyclone 10LP to catch data from AD9257. Data and frame clock coming form ADC are LVDS signals and frame clock is connected on clock capable LVDS pins. Frame clock is forwarded to PL...
ervoL's avatar
ervoL
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6 years ago

Hi KhaiY,

thank You very much for engagement.

Problem is meanwhile solved; it was a stupid copy paste mistake where I looked the data on the output of a register that comes after DDIO and that caused this one extra clock latency.

Best regards,

Lovre

P.S. I was a little ashamed, so I didn't write in the forum that the problem was solved, but I will do that next time.