Forum Discussion
New ContributorCyclone 10LP : Unable to read input frequency from any of the IO pins when input signal is powered-ON before cyclone 10LP power-on
Super Contributor"Timing constraints are not design for this code, since the code is working fine."
It doesn't matter if the design seems to be working fine. You *always* need to constrain a design with timing constraints in a .sdc file. Without it, there is no guarantee that anything output by the Fitter will always meet your timing requirements.
For Signal Tap, if you're trying to debug something that is happening just after programming the device, you can try using the power-up trigger feature. This will cause the logic analyzer to automatically start looking for one or more triggers immediately after device configuration but before you're able to start the logic analyzer in the .stp file. If the trigger occurs, the captured data is stored in the logic analyzer memory buffer and automatically transferred to the .stp file when you first start the logic analyzer. See the documentation for details on power-up trigger.
#iwork4intel
New ContributorHello
Thanks for your support,
i just shorted input signal to one of the test point(TP),
i found that input signal is not able to detect by C10LP at power-on state, i.e. their is no signal at the TP. when i reprogrammed by JTAG/power off complete set-up and power-on C10LP first and later input signal, C10LP can able to detect,i.e. signal at the TP same as the input signal.
In Pin planner this pin is declared as 3.3V_LVTTL, their are no modifications in assignment editor.
can you suggest some of the settings in quartus prime that how to detect the signal.
