Forum Discussion
New ContributorCyclone 10LP : Unable to read input frequency from any of the IO pins when input signal is powered-ON before cyclone 10LP power-on
Super ContributorCan you provide any code? That would be helpful.
Is the design meeting timing requirements? You're talking about kHz signals but it would still be useful to see what timing constraints you are using for your design.
As far as Signal Tap is concerned, when you say you are "unable to monitor", what exactly is happening with the tool that is not working as you expect? What are you using as the trigger for the tool?
#iwork4intel
New ContributorFor reading khz signal, we are using 25MHz as system input clock frequency and internally generating 160MHz using PLL.
Timing constraints are not design for this code, since the code is working fine. when input signal will power-on after some delay.
using signal tapping we are trying to monitor power-up problem and trying to monitor the each stage probing. since the problem is not able to recall it because of reprogramming of FPGA, when we reprogram FPGA it will start working/reading frequency.
