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RBach6's avatar
RBach6
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6 years ago

Cyclone 10GX eval board serdes pin mapping question

Hi, I designed a board with high speed adc,dac and clock on an fmc board to match with the fmc connector on the cyclone 10gx eval board. For the most part it is working good. I am running into an is...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
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6 years ago
Hello , Can you try to promote the reference clock (clock input) manually ? Here is the quartus prime setting assignment , set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to <name of toplevel reference clock input port> kindly let me know how it go ? Thank you , Regards, Sree
RBach6's avatar
RBach6
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6 years ago

Hi Sree,

thanks for the reply. I tried the following as per your suggestion

reference clock going to two different banks and two plls

one bank refclk->pll0->serdes(with 7 channels)

second bank refclk->pll1->serdes(with 2 channels)

and added the set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to <name of toplevel reference clock input port> in the qsf file

the compiler failed at the placement stage, reason being fitter can't place logic LVDS_CLOCK_TREE that is part of LVDS SERDES INTEL FPGA IP

it almost looks like, I won't be able to test this withe the existing set up. please let me know, if I can add any other constraints to bypass it

Thanks,

Ramakrishna