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PhilipJ451's avatar
PhilipJ451
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2 years ago

Cyclone 10 power-up latches up

Hi all, we have a number of designs that use the Cyclone 10CL025YE144 device. They are programmed by a Host CPU using PS mode. Occasionally we run up against a batch of devices that appear to get i...
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  • PhilipJ451's avatar
    PhilipJ451
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    2 years ago

    Hi Again,

    thank you for the information.

    I am familiar with Signal Tap, I use it quite often to examine what is going on in my logic design.

    My problem is that the FPGA is not allowing me to program it and as Signal Tap is compiled into my design I cannot get Signal Tap into the chip in order to debug with it.

    My question was, are there any "chip status" registers within the JTAG part of the chip that can be read via the USB-Blaster before the chip has been programmed to determine why the nSTATUS line (and it would seem all the other IO pins) remain low and sink current when the data-sheet says they should all remain in Hi-Z state.

    regards

    PhilipJ