New Contributor
New ContributorHi Zi,
First of all, thank you for your help and immediate response!
Secondly, I do not have any technical issues with the programming environment. I am just trying to thoroughly understand what is happening behind the Quartus automation and how to build my custom Verilog logic on top of a generated IP core. Let's narrow the scope of my question to the Ethenet IP core only.
Up to this point, I've managed to understand where the instantianted IP core spanws its files and locate the Top.v module. Now, in order to use Ethernet IP core, the documentation suggests running several TCL test scripts - for packet generation, monitoring, etc. As mentioned above, my actual "issue" is that I am using something without knowing what is exactly happening under hood. And that bothers me way too much.
So, my next goal is to manually send and receive a single Ethernet frame by adding my custom logic to the Top module (attached). Could you please help me with:
1) Some example code?
2) [even better] Some idea how to "debug" what is happening behind the TCL scripts? Do they generate any Verilog code that I can then review and modify to understand how the Ethernet Top.v module is utilised?
Thank you in advance!
