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Altera_Forum's avatar
Altera_Forum
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8 years ago

Cyclone 10 LP Clock input and data in different banks

Hi, I am new to Cyclone 10 LP device and plan to use 10CL016YU484C6G device in my design. I have a question related to clock pin and data pin connection for a source synchronous data bus. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

That sounds absolutely fine. I don't anticipate any problems with that. Constrain the interface appropriately and you shouldn't have any problems. Worst case (which I really don't envisage) you may need to instantiate a PLL - you may wish to do this anyway - to generate a phase adjusted local clock but I really don't anticipate the need for that.

Cheers,

Alex