Cyclone 10 GX PCIe pin setting

Dear Sir

I got a Cyclone 10 GX board.

I want to use the PCIe function.

So, I add the "Intel Arria 10/Cyclone 10 Hard IP for PCI Express" IP for PCIe function.

After generate the example verilog code, I got a Top module pcie_ed.v. (Gen1 X4)

I found it has a lot of input and output like below!!!

After I see the "https://www.intel.com/content/www/us/en/docs/programmable/683647/18-0/channel-and-pin-placement-for-the-gen1.html" information, I just know how to set xcvr_rx_inX andxcvr_tx_inX pin.

Could you please tell me, how can I set the pins ??

Thanks QQ!

input wire pcie_rstn_npor, // pcie_rstn.npor
input wire pcie_rstn_pin_perst, // .pin_perst
input wire [31:0] hip_ctrl_test_in, // hip_ctrl.test_in
input wire hip_ctrl_simu_mode_pipe, // .simu_mode_pipe
input wire pipe_sim_only_sim_pipe_pclk_in, // pipe_sim_only.sim_pipe_pclk_in
output wire [1:0] pipe_sim_only_sim_pipe_rate, // .sim_pipe_rate
output wire [4:0] pipe_sim_only_sim_ltssmstate, // .sim_ltssmstate
output wire [2:0] pipe_sim_only_eidleinfersel0, // .eidleinfersel0
output wire [2:0] pipe_sim_only_eidleinfersel1, // .eidleinfersel1
output wire [2:0] pipe_sim_only_eidleinfersel2, // .eidleinfersel2
output wire [2:0] pipe_sim_only_eidleinfersel3, // .eidleinfersel3
output wire [1:0] pipe_sim_only_powerdown0, // .powerdown0
output wire [1:0] pipe_sim_only_powerdown1, // .powerdown1
output wire [1:0] pipe_sim_only_powerdown2, // .powerdown2
output wire [1:0] pipe_sim_only_powerdown3, // .powerdown3
output wire pipe_sim_only_rxpolarity0, // .rxpolarity0
output wire pipe_sim_only_rxpolarity1, // .rxpolarity1
output wire pipe_sim_only_rxpolarity2, // .rxpolarity2
output wire pipe_sim_only_rxpolarity3, // .rxpolarity3
output wire pipe_sim_only_txcompl0, // .txcompl0
output wire pipe_sim_only_txcompl1, // .txcompl1
output wire pipe_sim_only_txcompl2, // .txcompl2
output wire pipe_sim_only_txcompl3, // .txcompl3
output wire [31:0] pipe_sim_only_txdata0, // .txdata0
output wire [31:0] pipe_sim_only_txdata1, // .txdata1
output wire [31:0] pipe_sim_only_txdata2, // .txdata2
output wire [31:0] pipe_sim_only_txdata3, // .txdata3
output wire [3:0] pipe_sim_only_txdatak0, // .txdatak0
output wire [3:0] pipe_sim_only_txdatak1, // .txdatak1
output wire [3:0] pipe_sim_only_txdatak2, // .txdatak2
output wire [3:0] pipe_sim_only_txdatak3, // .txdatak3
output wire pipe_sim_only_txdetectrx0, // .txdetectrx0
output wire pipe_sim_only_txdetectrx1, // .txdetectrx1
output wire pipe_sim_only_txdetectrx2, // .txdetectrx2
output wire pipe_sim_only_txdetectrx3, // .txdetectrx3
output wire pipe_sim_only_txelecidle0, // .txelecidle0
output wire pipe_sim_only_txelecidle1, // .txelecidle1
output wire pipe_sim_only_txelecidle2, // .txelecidle2
output wire pipe_sim_only_txelecidle3, // .txelecidle3
output wire pipe_sim_only_txdeemph0, // .txdeemph0
output wire pipe_sim_only_txdeemph1, // .txdeemph1
output wire pipe_sim_only_txdeemph2, // .txdeemph2
output wire pipe_sim_only_txdeemph3, // .txdeemph3
output wire [2:0] pipe_sim_only_txmargin0, // .txmargin0
output wire [2:0] pipe_sim_only_txmargin1, // .txmargin1
output wire [2:0] pipe_sim_only_txmargin2, // .txmargin2
output wire [2:0] pipe_sim_only_txmargin3, // .txmargin3
output wire pipe_sim_only_txswing0, // .txswing0
output wire pipe_sim_only_txswing1, // .txswing1
output wire pipe_sim_only_txswing2, // .txswing2
output wire pipe_sim_only_txswing3, // .txswing3
input wire pipe_sim_only_phystatus0, // .phystatus0
input wire pipe_sim_only_phystatus1, // .phystatus1
input wire pipe_sim_only_phystatus2, // .phystatus2
input wire pipe_sim_only_phystatus3, // .phystatus3
input wire [31:0] pipe_sim_only_rxdata0, // .rxdata0
input wire [31:0] pipe_sim_only_rxdata1, // .rxdata1
input wire [31:0] pipe_sim_only_rxdata2, // .rxdata2
input wire [31:0] pipe_sim_only_rxdata3, // .rxdata3
input wire [3:0] pipe_sim_only_rxdatak0, // .rxdatak0
input wire [3:0] pipe_sim_only_rxdatak1, // .rxdatak1
input wire [3:0] pipe_sim_only_rxdatak2, // .rxdatak2
input wire [3:0] pipe_sim_only_rxdatak3, // .rxdatak3
input wire pipe_sim_only_rxelecidle0, // .rxelecidle0
input wire pipe_sim_only_rxelecidle1, // .rxelecidle1
input wire pipe_sim_only_rxelecidle2, // .rxelecidle2
input wire pipe_sim_only_rxelecidle3, // .rxelecidle3
input wire [2:0] pipe_sim_only_rxstatus0, // .rxstatus0
input wire [2:0] pipe_sim_only_rxstatus1, // .rxstatus1
input wire [2:0] pipe_sim_only_rxstatus2, // .rxstatus2
input wire [2:0] pipe_sim_only_rxstatus3, // .rxstatus3
input wire pipe_sim_only_rxvalid0, // .rxvalid0
input wire pipe_sim_only_rxvalid1, // .rxvalid1
input wire pipe_sim_only_rxvalid2, // .rxvalid2
input wire pipe_sim_only_rxvalid3, // .rxvalid3
input wire pipe_sim_only_rxdataskip0, // .rxdataskip0
input wire pipe_sim_only_rxdataskip1, // .rxdataskip1
input wire pipe_sim_only_rxdataskip2, // .rxdataskip2
input wire pipe_sim_only_rxdataskip3, // .rxdataskip3
input wire pipe_sim_only_rxblkst0, // .rxblkst0
input wire pipe_sim_only_rxblkst1, // .rxblkst1
input wire pipe_sim_only_rxblkst2, // .rxblkst2
input wire pipe_sim_only_rxblkst3, // .rxblkst3
input wire [1:0] pipe_sim_only_rxsynchd0, // .rxsynchd0
input wire [1:0] pipe_sim_only_rxsynchd1, // .rxsynchd1
input wire [1:0] pipe_sim_only_rxsynchd2, // .rxsynchd2
input wire [1:0] pipe_sim_only_rxsynchd3, // .rxsynchd3
output wire [17:0] pipe_sim_only_currentcoeff0, // .currentcoeff0
output wire [17:0] pipe_sim_only_currentcoeff1, // .currentcoeff1
output wire [17:0] pipe_sim_only_currentcoeff2, // .currentcoeff2
output wire [17:0] pipe_sim_only_currentcoeff3, // .currentcoeff3
output wire [2:0] pipe_sim_only_currentrxpreset0, // .currentrxpreset0
output wire [2:0] pipe_sim_only_currentrxpreset1, // .currentrxpreset1
output wire [2:0] pipe_sim_only_currentrxpreset2, // .currentrxpreset2
output wire [2:0] pipe_sim_only_currentrxpreset3, // .currentrxpreset3
output wire [1:0] pipe_sim_only_txsynchd0, // .txsynchd0
output wire [1:0] pipe_sim_only_txsynchd1, // .txsynchd1
output wire [1:0] pipe_sim_only_txsynchd2, // .txsynchd2
output wire [1:0] pipe_sim_only_txsynchd3, // .txsynchd3
output wire pipe_sim_only_txblkst0, // .txblkst0
output wire pipe_sim_only_txblkst1, // .txblkst1
output wire pipe_sim_only_txblkst2, // .txblkst2
output wire pipe_sim_only_txblkst3, // .txblkst3
output wire pipe_sim_only_txdataskip0, // .txdataskip0
output wire pipe_sim_only_txdataskip1, // .txdataskip1
output wire pipe_sim_only_txdataskip2, // .txdataskip2
output wire pipe_sim_only_txdataskip3, // .txdataskip3
output wire [1:0] pipe_sim_only_rate0, // .rate0
output wire [1:0] pipe_sim_only_rate1, // .rate1
output wire [1:0] pipe_sim_only_rate2, // .rate2
output wire [1:0] pipe_sim_only_rate3, // .rate3
input wire xcvr_rx_in0, // xcvr.rx_in0
input wire xcvr_rx_in1, // .rx_in1
input wire xcvr_rx_in2, // .rx_in2
input wire xcvr_rx_in3, // .rx_in3
output wire xcvr_tx_out0, // .tx_out0
output wire xcvr_tx_out1, // .tx_out1
output wire xcvr_tx_out2, // .tx_out2
output wire xcvr_tx_out3 // .tx_out3