Occasional Contributor
Super ContributorHi,
I don't know what causes failure of LVDS link in your design, two points are however clear:
- it's normal operation to see spurious signals on open LVDS input as well as continuous H or L level. Differential input buffer has no hysteresis or offset and therefore shows received noise as signal. We even see false valid 10b/8b packets, altough with very low prohability.
- your "differential interconnection modification" is not confirming with Cyclone 10 GX LVDS termination requirements.
If you absolutely need to suppress spurious signals at open input, you may try to add a small DC offset (e.g. 50 - 100 mV) to input bias, although it causes an input asymmetry and decreases SERDES timing margin. You can start with Your figure 5 scheme and add respective pull-up/down resistors.
Occasional ContributorHi FvM,
Yeah, we know that LVDS link may not be stable when LVDS is open. Question is that the issue happened when LVDS link was closed. Then we captured it from closed link to open link. As figure 4 shows, there are total 4 links in our case. We encountered similar issue on link 1 and link 3 at the very beginning. We have resolved them. Now we have the similar issue on link 0. We ignore the issue on link 0 because we can't capture it when we use 100MHz sampling clock for SignalTap II. However, we collected unwanted data from link 0 when source board was plugged to link 1, as figure 9.
figure 9: link 0 can receive unwanted data when it opens
The link 0 was capture clean when SiganlTap II run under 100 MHz, however, the unwanted pulse can be detected when SignalTap II run under 500 MHz. So the unwanted noise pulse width should be around from 2 ns to 4 ns.
As you can see in figure 9, link 2 and link 3 are clean in the same situation. By the same way, we also proved that link 1 is same clean as link 2&3. We are continuing to investigate this issue, but currently we have no clue. We hope someone here can give us some hints for this.
