Forum Discussion

New Contributor

5 years ago

Cyclone 10 GX LVDS input voltage tolerance

What is the absolute maximum pin voltage, and differential voltage, for an LVDS input with 1.8V VCCIO? Referring to the datasheet C10GX51002 2018.06.15, Table 13 says recommended max Vi = 2.19V, bu...

ShafiqY_Intel

Frequent Contributor

5 years ago

Hi JB_ISDI,

The LVDS I/O pins can tolerate a maximum of 10 mA per pin and a total of 100 mA per I/O bank.

The voltage level of the LVDS I/O pin must not exceed 1.89 V.

You may refer to following document for more details:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an692.pdf

Regards,

Matt

Forum Discussion

Cyclone 10 GX LVDS input voltage tolerance

Recent Discussions

Issue with configuring EPCQ64A & Cyclone10LP using NiosV as processor.

Agilex5 A5EB013BB23BE4S BSDL

Quartus Prime Pro 25.1 fatal error during fitter: Windows "Efficiency mode" required

FFVH-ICS-0923-00（1SM21BHU2F53E2VGNE）failed at ESS-HOT test

JTAG Chain Broken on Agilex 7-I Dev Kit