Forum Discussion

designEngineer's avatar
designEngineer
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Cyclone 10 GX DDR interface timing / constraint issue

I am trying to meet timing on a source synchronous edge aligned DDR interface with a Cyclone 10 GX. The interface fails timing but I think the setup relationship from the DDIO output to the first reg...
designEngineer's avatar
designEngineer
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

@KennyT_Intel​

I have replied to your email trail since I have some follow up questions but have not heard back. Are you still supporting this issue and if so did you receive my follow up questions?

Thanks!