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designEngineer
Occasional Contributor
Occasional ContributorCyclone 10 GX DDR interface timing / constraint issue
I am trying to meet timing on a source synchronous edge aligned DDR interface with a Cyclone 10 GX. The interface fails timing but I think the setup relationship from the DDIO output to the first reg...
sstrell
Super Contributor
Super ContributorFor a DDR input, you don't use the multicycle of 0. That's only for edge-aligned DDR output.
The online training explains this much better than the app note:
https://www.intel.com/content/www/us/en/programmable/support/training/course/oddr1000.html
#iwork4intel
