New ContributorCyclone 10 GX Clock Skew from the Same IOPLL
Background:
I'm doing some signal processing design with 300MHz main clock, but part of my pipeline will require to run all M20K at 600MHz to have enough bandwidth, so I was trying to implement a 1:2 and a 2:1 gearbox to raise the clock speed during the critical path. However the clock skew makes CDC very challenging.
My clock setup:
I have external 100MHz(clkin) feed into IOPLL0 to generate quality 100MHz(refclk), then feed that refclk into IOPLL1, running direct compensating mode with 600MHz(clk_2x) and 300MHz(clk) output. Both outputs distributed by GCLK.
As the faster clock is 600MHz, I have about 1.666ns timing budget. The estimated skew from within the IOPLL1 is around +-0.2ns, which matches the IOPLL jitter performance specification. However the estimated skew from clock path is around +-0.5ns. These alone ate up pretty much all the timing budget.
Does that sound about right or the Timing Analyzer is being too pessimistic? I'm a little bit surprised because both clocks are generated from the same IOPLL and feed into GCLK network from the neighbor CKLCTRL cells.
Alternative setup:
I also tried using IOPLL's normal compensation mode. So that I have:
100MHz(clkin) --> IOPLL0(direct compensation) --> 300MHz(clk) --> IOPLL1(normal compensation) --> 600 MHz (clk_2x)
But then I'm seeing even more clock skew in 5ns range!
Question:
* Where can I find the specification on the GCLK propagation / skew characteristics?
* If the variation between individual GCLK nets is indeed that much different, is there a way to somehow generate very well aligned (< 0.2ns skew) synchronized clocks?
* How would you program 1:2 2:1 gearboxes that works at 300MHz:600MHz?
