Cyclone 10 GX Clock Skew from the Same IOPLL

Hi,

First thing I would suggest is to reduce the number of IOPLL in path. This will reduce the jitter introduced by the PLL itself. Each IOPLL in Cyclone 1 GX can generate up to nine output clocks at the same time. You can generate 100MHz, 300MHz and 600MHz from one IOPLL only. Use the Normal compensation mode.

For the CDC, you should always use the domain crossing techniques such as double flop synchronizer or pulse stretcher or FIFO etc. to make sure that the crossing is correct. Other way that you can use is to define False Path between the two domains. Hope this helps.

Regards