Cyclone 10 GX Clock Skew from the Same IOPLL

That is not true. Even Cyclone V can do better than that. Cyclone 10 GX could clock up to fMAX = 644MHz, limited by minimal pulse width: https://www.intel.com/content/www/us/en/docs/programmable/683828/current/clock-tree-specifications.html

That said, it is true that the number of logic layers would be severely limited at that frequency, the design will need to be heavily pipelined. That's why I target my design at 300MHz with only the memory intensive part running at 600MHz.

I did try to fiddle a few settings afterwards. I realized that my Timing Analyzer calculated for both the fastest and the slowest speed grade. It was a mistake as I don't really intend to use slower speed grade devices. My product is intended to be used indoor with good thermal solution. After changing the settings to consider only the fastest speed grade I was able to get the 600-->300 CDC to work. Still need to add some delay to satisfy hold, but at least now I have plenty time margin for setup.