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trchen's avatar
trchen
Icon for New Contributor rankNew Contributor
4 years ago

Cyclone 10 GX Clock Skew from the Same IOPLL

Background: I'm doing some signal processing design with 300MHz main clock, but part of my pipeline will require to run all M20K at 600MHz to have enough bandwidth, so I was trying to implement a 1...
Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

We did not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you