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JLee25's avatar
JLee25
Icon for Contributor rankContributor
6 years ago

Cyclone 10 GX 3V IO Voltage

Hi community, I have a new project based on C10 GX and I am debugging the IO problem. The device is 10GX220YF672, the IO bank 2L was design to interface 3V IO. I download a counter design to ver...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Johnson Lee,

No tri-stated is needed from external pin. During FPGA power up, the pin itself will tri-state for used pin. Meanwhile for unused pin, you will need to do some setting in Quartus to enable tri-stating.

To do so, go to "Assignments" -> "Device" -> "Device and pin info" -> "Unused pin" -> "As input tri-stated with weak pull up"

Thank You