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JLee25's avatar
JLee25
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6 years ago

Cyclone 10 GX 3V IO Voltage

Hi community, I have a new project based on C10 GX and I am debugging the IO problem. The device is 10GX220YF672, the IO bank 2L was design to interface 3V IO. I download a counter design to ver...
  • JLee25's avatar
    JLee25
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    6 years ago

    Hi YL,

    Thank you for reply.

    Yes, I did set the IO standard to 3.0V.

    Attached is the qar file for your reference.

    I test 2 boards with this configuration.

    Both show the same status,

    before config, gpio_0 is 3V, led_0 is 0.7V. After config, gpio_0 switch between 3V/ 0 V. led_0 is 0.9V/ 0V.

    Regards,

    Johnson

    • JLee25's avatar
      JLee25
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      6 years ago

      Hi YT,

      I just found the clock was not operated properly, amplitude is small..

      I will check it and see if this is the root cause!

      Thank you!

      Regards,

      Johnson

  • JLee25's avatar
    JLee25
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    6 years ago

    Hi YT,

    I have a question on the reference file.

    From the table below, it means the external IO pin should be in Tristate during FPGA boot up ?

    If above rule can’t be followed, what will happen to the device?

    And what should I do to prevent this?

    Boot external devices later than FPGA ?

    Please comment.

    Thank you!

    Best Regards,

    Johnson Lee