Contributor
Regular ContributorHi Johnson Lee,
Just want to check, have you set the IO Standard of Bank 2L to 3.0V?
It is not a problem for an external devices that boot earlier than FPGA if you obey the pin state as shown in the user guide:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf (Page 273).
For example, LVDS I/O banks need to be tristated (Setting in Quartus) while power up and vice versa.
Thank You.
ContributorHi YL,
Thank you for reply.
Yes, I did set the IO standard to 3.0V.
Attached is the qar file for your reference.
I test 2 boards with this configuration.
Both show the same status,
before config, gpio_0 is 3V, led_0 is 0.7V. After config, gpio_0 switch between 3V/ 0 V. led_0 is 0.9V/ 0V.
Regards,
Johnson
ContributorHi YT,
I just found the clock was not operated properly, amplitude is small..
I will check it and see if this is the root cause!
Thank you!
Regards,
Johnson
ContributorHi YT,
I have a question on the reference file.
From the table below, it means the external IO pin should be in Tristate during FPGA boot up ?
If above rule can’t be followed, what will happen to the device?
And what should I do to prevent this?
Boot external devices later than FPGA ?
Please comment.
Thank you!
Best Regards,
Johnson Lee
