CVP on Stratix V

Hi

I want to use the Configure Via Protocol (CVP) in a system I'm designing. Using the reference design and driver provided by Altera (https://www.altera.com/support/support-resources/support-centers/devices/cfg-index/cfg-via-protocol.html) I've been able to set up my system. Now I would like to configure and use my FPGA with new custom bitstreams at runtime.

my problem is the following: What interface should my custom bitstreams implement to allow to read results from my FPGA and to write to it? How can communicate from a CPU with my new designs? The reconfiguration of the FPGA is no longer a problem for me but I'm still not sure about how to communicate with new design when I update the application running on the FPGA.

Can anyone help? Thanks:(