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ARaja4's avatar
ARaja4
Icon for New Contributor rankNew Contributor
7 years ago

CVP on Cyclone V

Hi, I have been trying to make CVP on Cyclone V 5CGTFD7C5U19C7 FPGA. My requirement is Gen2 Lane2 PCIE interface with CVP enabled. My FPGA board has Gen2 Lane2(X2) M.2 interface. I downloaded alter...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

I guess this is a known issue that x2 does not work in CVP. The following is from Intel KB on CvP:

https://www.intel.com/content/www/us/en/programmable/documentation/nik1412546950394.html#nik1412546929892

Known Issues and Solutions

  1. CvP designs with Gen1 x2 configurations fail to link up after loading the periphery image. One way to work around this issue is to use Gen1 x4 configuration and let the link downtrain to Gen1 x2.
  2. You cannot use the Transceiver Reconfiguration Controller IP Core in CvP update mode. Refer to Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core for more a workaround.