New Contributor
Regular ContributorHi Allen Rubis,
As per the IEEE standard, the external PHY device is required to configure as per their datasheet via the MDIO interface. From soft TSE IP perspective, to access external PHY device, you have to write the PHY address at mdio_addr 1 register (offset 0x10), and followed by the transactions data at MDIO space 1 (offset 0xA0 to 0XBF). Please refer to the TSE IP user guide below for more detail:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf
The design you are referring to is from rocketboard and that is not using NIOS II, the control port of TSE IP is connected to HPS as you can see. Hence, this is require to go through the HPS design flow to update the driver for difference external PHY. You have to check whether the Marvell 88E1512 has been defined in the driver, if not, you can define the parameter of Marvell 88E1512 in the driver by yourself, or you can refer to the newer version of driver that may already defined by someone else (https://github.com/altera-opensource/u-boot-socfpga).
To determine if the Marvell 88E1512 is defined, after you have generated the uboot, you can check the following files.
Marvell.c file:
/drivers/net/phy/
socfpga_common.c
board/altera/socfpga_arria10
Regards -SK Lim
