Crossing clock domains?

Ok - thats fair enough

Because the CPU clock is so much slower than the FPGA clock, you could easily just sample the CPU clock and detect rising edges as enables in the FPGA clock domain (as anakha has already suggested).

signal cpu_clk_resync : std_logic_vector(3 downto 0);
signal cpu_clk_en     : std_logic;
process(fpga_clk)
begin
  if rising_edge(fpga_clk) then
    cpu_clk_resync <= cpu_clk_resync(2 downto 0) & cpu_clk;
    
    if      cpu_clk_resync(2) = '1' 
        and cpu_clk_resync(3) = '0' 
        and cpu_clk_resync(1) = '1'     -- ensure it really is stable and not metastable/bouncing
    then
        cpu_clk_en  <= '1';
    end if;
    
  end if;
end process;

Then you can safely use any properly synchronised data