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Altera_Forum
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10 years ago

Crossing clock domains?

I'm just learning about FPGAs (using VHDL) and have encountered metastability problems which I'm fairly certain are due to crossing clock domains. I have made a VGA controller (on a DE1 Cyclone...
Altera_Forum's avatar
Altera_Forum
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10 years ago

I had thought of that, but the CPU clock is generated elsewhere and that's not easy/possible to change, and it may vary - it might actually be 0.888625 MHz, or it might be 0.894886 MHz depending on the original computer model (or it may occasionally be double that if running in 'fast' mode), so I can't even easily generate a 'fake' clock in the FPGA and sync it with the actual clock.

(I'm not building my own 6809 computer with an FPGA attached - I'm using the FPGA as a plug-in peripheral for an existing 6809-based 1980's computer (Dragon 32/64/Tandy Coco))