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Altera_Forum
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10 years ago

Crossing clock domains?

I'm just learning about FPGAs (using VHDL) and have encountered metastability problems which I'm fairly certain are due to crossing clock domains. I have made a VGA controller (on a DE1 Cyclone...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

The easiest way to fix this would be to run the CPU at 108MHz, but generate a 0.9Mhz enable signal, so that the CPU is only active at the correct clock speed. Then there is only 1 clock domain and there are no clock domain crossing issues.