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Altera_Forum
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10 years ago

Crossing clock domains?

I'm just learning about FPGAs (using VHDL) and have encountered metastability problems which I'm fairly certain are due to crossing clock domains. I have made a VGA controller (on a DE1 Cyclone...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thanks. That's what I thought - I just wanted to check I was understanding the problem reasonably correctly. I'm not entirely sure how to solve the problem in all cases, but I think I've got it for this particular case.

I've just got to try and rework my design to be less combinational and more synchronous against a single clock (hopefully without having to start from scratch) :-)