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Altera_Forum
Honored Contributor
Honored ContributorCrossing clock domains?
I'm just learning about FPGAs (using VHDL) and have encountered metastability problems which I'm fairly certain are due to crossing clock domains. I have made a VGA controller (on a DE1 Cyclone...
Altera_ForumHonored Contributor
Honored ContributorYes. Based on your description, you can synchronize your Q clock signal and generate an "Enable" pulse in the fast clock domain. This should be sufficient because you CPU hold time is very long. and less than the time required to synchronize the Q Clock and detect an edge.
If the address/data hold time was < than the time required to synchronize the control signal, then you need to register the bus in the slow domain first, so you can ensure it is stable. Pete
