Crossing clock domains?

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I'm just learning about FPGAs (using VHDL) and have encountered metastability problems which I'm fairly certain are due to crossing clock domains.

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You are already ahead of the game if you at least know about metastability! Good job!

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Currently, I have the 108MHz FPGA clock running state machines etc, with the CPU clock directly interacting with them to affect state transitions. I believe this is a big crime (forgive me, I'm still learning)! (Debugging with a logic analyser shows things like the state machines ending up in weird and unexpected states)

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I'll forgive you this time :)

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So, to solve the problem of crossing clock domains, would it be OK to just pass the micro's CPU clock signals through a couple of clocked (using the 108MHz clock) registers? I'd end up with ~20ns delay, but to a 1MHz CPU that's not going to be a problem :-) Would that reduce the metastability problems substantially?

I don't think I need anything more complicated, such as proper 'handshaking'

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It depends on what signals are crossing, and how the are used.

If you just have say one "Enable" signal, a single double or triple register synchronizer may be all you need.

In general if you have and address/data bus, the full bus needs to be synchronized. This can be through a dual port/dual clock fifo, or through special a special handshake where you register the bus in one domain, and send a single signal to the other domain that registers the bus in the other domain.

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I don't think I'll need to synchronise the micro's address/data bus etc because they're all guaranteed to be set up before the CPU clock anyway.

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It depends on how it is used. If the bus goes to the other domain the individual bits can be interpreted (registered) at different high speed clocks, unless the "Enable" signal is properly synchronized.

Pete