CROSS CLOCK vhdl

It should be understood that this...

--- Quote Start ---

Underflow and overflow circuitry protections are enabled by default to prevent FIFO data corruption. Turning on the option from the FIFO

MegaWizard plug-in disables the protection circuitry.

When the protection circuitry is disabled, writing to a full FIFO can corrupt the FIFO dataand reading from an empty FIFO can return unknown data and produce unpredictable future results; however, when the protection circuitry is disabled, the FIFO megafunction uses fewer device resources.

--- Quote End ---

does not mean that you shouldn't empty or fill a FIFO. You just can't write to a full FIFO or read from an empty FIFO without corrupting the contents. And the obvious reason why is that the read or write counter will roll over.

So, you can either instruct the megawizard to perform protection for you or you can perform the protection yourself (which is what I typically do). Typically you have the empty and full signals anyway so you can perform flow control. It's certainly not hard to gate your write and read signals with the full and empty signals.

Jake