CROSS CLOCK vhdl

It seems that altera has two remediies for their old warning:

1) an almost_empty flag

2) protection circuitry(extra logic)

This what they say(dc fifo user guide)

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Underflow and overflow circuitry protections are enabled by default to prevent FIFO data corruption. Turning on the option from the FIFO

MegaWizard plug-in disables the protection circuitry.

When the protection circuitry is disabled, writing to a full FIFO can corrupt the FIFO dataand reading from an empty FIFO can return unknown data and produce unpredictable future results; however, when the protection circuitry is disabled, the FIFO megafunction uses fewer device resources.

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